User Manual version 2207
APOLLO 120/150 III
7-118
u SDRAM/VCM CAS LATENCY
When synchronous DRAM is installed, the number of clock
cycles of CAS latency depends on the DRAM timing.
The Choice: 2, 3 or SPD
u SDRCLK CONTROL
This item controls the phase of SDRCLK that lags behind
SDCLK.
The choice: Enabled or Disabled.
u SDWCLK CONTROL CS#/CKE
This item controls the phase of SDWCLK used for chip set
select signals pin that lags ahead SDCLK.
The choice: Enabled or Disabled.
u SDWCLK CONTROL MA/SRAS
This item controls the phase of SDWCLK used for MA/ SRAS
signals that lags ahead SDCLK.
The choice: +5.0ns~-2.5ns (Default 0.0ns)
u SDWCLK CONTROL DQM/MD
This item controls the phase of SDWCLK used for DQM/MD
signals that lags ahead SDCLK.
The choice: +5.0ns~-2.5ns (Default 0.0ns)
u EGMRCLK CONTROL
This item controls the phase of EGMRCLK that lags behind
SDCLK.
The choice: -1.0ns~+6.5ns (Default 0.0ns)
u EGMWCLK CONTROL
This item controls the phase of EGMWCLK that lags ahead
SDCLK.
The choice: +5.0ns~-2.5ns (Default 0.0ns)
