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SM7100 Programming 31
Control Register - Read and Write (continued)
D1
Front Panel
Open
Signal
Polarity Bit
0 = Non-inverted Front Panel Open signal polarity
1 = Inverted Front Panel Open signal polarity
Pon state = 0
Non-inverted: If set in pulse mode, the Front Panel Open signal will generate a
reset pulse on a falling edge. If set in level mode, the Front Panel Open signal will
generate a reset signal on a low input signal.
Inverted: If set in pulse mode, the Front Panel Open signal will generate a reset
pulse on a rising edge. If set in level mode, the Front Panel Open signal will
generate a reset signal on a high input signal.
D0
Front Panel
Open
Signal
Operation
Select Bit
0 = Pulse mode
1 = Level mode
Pon state = 0
Pulse mode: An edge seen at the Front Panel Open signal pin will generate a reset
pulse that may be used to reset system relays. The pulse is of approximately 300 ns
duration.
Level mode: A level present on the Front Panel Open signal pin will generate a
reset signal that may be used to reset system relays. This signal will remain active
as long as the input is active.
On the front panel of most SMIP II plug-in modules, there are two pins for access
to the Front Panel Open signal of the module. These are the Front Panel Open
signal pin and a ground reference pin. The purpose of the Front Panel Open signal
is to allow user access to a configurable interlock feature that will reset all of the
SMIP II system relays. The Front Panel Open signal may be used to reset the relays
only on the module, which initiated the Front Panel Open signal fault condition. It
also may be used to broadcast to all the other SMIP II plug-in modules installed in
a SMIP II Interface Module via what is called the Openbus. Any plug-in module
may be programmed to drive and/or listen to the Openbus. The Openbus signal
may also be used to generate a wider chassis level fault signal via the TTL Trigger
Bus (see the register definitions for A16 address space). The Front Panel Open
signal is meant to be driven by either a switch closure or TTL/CMOS logic gate. It
is pulled high on the module.