DM9161B
10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver
Final 22
Version: DM9161B-12-DS-F01
January 31, 2008
8. MII Register Description
AD
D
Name 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset Loop
back
Speed
select
Auto-N
Enable
Power
Down
Isolate Restart
Auto-N
Full
Duplex
Coll.
Test
Reserved 00 CONTROL
0 0 1 1 0 0 0 1 0 000_0000
T4
Cap.
TX FDX
Cap.
TX HDX
Cap.
10 FDX
Cap.
10 HDX
Cap.
Reserved Pream.
Supr.
Auto-N
Compl.
Remote
Fault
Auto-N
Cap.
Link
Status
Jabber
Detect
Extd
Cap.
01 STATUS
0 1 1 1 1 0000 1 0 0 1 0 0 1
02 PHYID1 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1
PHYID2 1 0 1 1 1 0 Model No. Version No. 03
001011 0000
04 Auto-Neg.
Advertise
Next
Page
FLP Rcv
Ack
Remote
Fault
Reserved FC
Adv
T4
Adv
TX FDX
Adv
TX HDX
Adv
10 FDX
Adv
10 HDX
Adv
Advertised Protocol Selector Field
05 Link Part.
Ability
LP
Next
Page
LP
Ack
LP
RF
Reserved LP
FC
LP
T4
LP
TX FDX
LP
TX HDX
LP
10 FDX
LP
10 HDX
Link Partner Protocol Selector Field
06 Auto-Neg.
Expansion
Reserved Pardet
Fault
LP Next
Pg Able
Next Pg
Able
New Pg
Rcv
LP AutoN
Cap.
16 Specified
Config.
BP
4B5B
BP
SCR
BP
ALIGN
BP_ADP
OK
Repeater TX FEF_EN RMII_E
N
Force
100LNK
TST_SE
L0
LEDCO
L_SEL
RPDCTR
-EN
Reset
St. Mch
Pream.
Supr.
Sleep
mode
Remote
LoopOut
17 Specified
Conf/Stat
100
FDX
100
HDX
10
FDX
10 HDX Reserve
d
Reverse
d
Reverse
d
PHY ADDR [4:0] Auto-N. Monitor Bit [3:0]
18 10T
Conf/Stat
Rsvd LP
Enable
HBE
Enable
SQUE
Enable
JAB
Enable
10T
Serial
Reserved Polarity
Reverse
19 PWDOR Reserved PD10DR
V
PD100l PDchip PDcrm PDaeq PDdrv PDecli PDeclo PD10
20 Specified
config
TSTSE1 TSTSE2 FORCE_
TXSD
FORCE_
FEF
Reserved MDIX_C
NTL
AutoNeg
_dlpbk
Mdix_fix
Value
Mdix_do
wn
MonSel1 MonSel0 Rmii_acc
u
PD_valu
e
21 MDINTR Int_sts Reserve
d
Reserve
d
Reverse
d
Fdx_msk Spd_msk Lnk_msk Int_msk Reserve
d
Reserve
d
Reverse
d
Fdx_chg Spd_chg Lnk_chg Reserve
d
Int_sts
22 RCVER Receiver Error Counter
23 DIS_connec
t
Reversed Disconnect_counter
24 RSTLH Lh_led_
mode
Lh_mdint
r
Lh_cabst
s
Lh_isolat
e
Lh_rmii Lh_seril1
0
Lh_repea
ter
Lh_testm
ode
Lh_op2 Lh_op1 Lh_op0 Lh_phya
d4
Lh_phya
d3
Lh_phya
d2
Lh_phya
d1
Lh_phya
d0
29 PSCR Reserve
d
Reserve
d
Reserve
d
Reserve
d
preamble
x
amplitud
e
TX_PW
R
Reserve
d
Reserve
d
Reserve
d
Reserve
d
Reserve
d
Reserve
d
Reserve
d
Reserve
d
Reserve
d
Key to Default
In the register description that follows, the default
column takes the form:
<Reset Value>, <Access Type> / <Attribute(s)>
Where：
<Reset Value>:
1 Bit set to logic one
0 Bit set to logic zero
X No default value
(PIN#) Value latched in from pin # at reset
<Access Type>:
RO = Read only
RW = Read/Write
<Attribute (s)>:
SC = Self clearing
P = Value permanently set
LL = Latching low
LH = Latching high
