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PD30500, 30500A, 30500B
11
Data Sheet U12031EJ3V0DS00
Pin Name I/O Function
Int (0:5) Input Interrupt.
General-purpose processor interrupt requests whose input statuses can be confirmed by
bits 15 through 10 of cause register.
NMI Input Non-maskable interrupt.
Interrupt request that cannot be masked.
ColdReset Input Cold reset.
Signal initializing the internal status of the processor. Inactivate this signal in synchroniza-
tion with SysClock.
Reset Input Reset.
Signal generating a reset exception, without initializing the internal status of the processor.
Inactivate this signal in synchronization with SysClock.
SysClock Input System clock.
Clock input signal to processor.
BigEndian Input Endian mode setting.
This signal sets the endian mode of the system interface.
When setting the endian mode with this signal, specify little endian with the data from the
ModeIn pin that is input at reset.
To set the endian mode with the data from the ModeIn pin, fix this signal to 0.
BigEndian Bit 8 of boot mode Mode
11 —
1 0 Big endian
0 1 Big endian
0 0 Little endian
ModeClock Output Boot mode clock.
Successive boot mode data clock output resulting from dividing SysClock by 256.
Modeln Input Boot mode data input.
Input of initialization bit stream.
VDDOk Input VDD and VDDIO
Note
are valid.
Signal indicating that the voltage supplied to the VR5000 is 3.135 V or higher for 100 ms,
and that that status is stabilized. When VDDOk is asserted active, the VR5000 starts an
initialization sequence.
VDDP – PLL VDD.
Power supply for internal PLL.
GNDP – PLL GND.
Ground for internal PLL.
VDD –• VR5000
Positive power supply pin (3.3 V)
• VR5000A
Power supply pin for core (2.5 V)
• VR5000B
Power supply pin for core (1.8 V)
VDDIO
Note
– Power supply pin for I/O (3.3 V)
GND – Ground pin.
Note VDDIO is only for VR5000A and VR5000B.