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PD30500, 30500A, 30500B
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Data Sheet U12031EJ3V0DS00
Capacitance
Parameter Symbol Condition MIN. MAX. Unit
Input capacitance CIn 5pF
Output capacitance Cout 7pF
AC Characteristics (TC = 0 to +70 °C (PGA Package), TC = 0 to +85 °C (BGA Package), VDD = 3.3 V ±5 %)
Clock parameter
Parameter Symbol Condition MIN. MAX. Unit
System clock high-level width tCH 3.0 ns
System clock low-level width tCL 3.0 ns
System clock frequency
Note 1, 2
150 MHz 20 75 MHz
180 MHz 20 90 MHz
200 MHz 20 100 MHz
System clock cycle tCP 150 MHz 13.3 50 ns
180 MHz 11.1 50 ns
200 MHz 10 50 ns
System clock jitter tji System clock frequency > 66 MHz ±125 ps
System clock frequency ≤ 66 MHz ±250 ps
System clock rise time tCR 2.0 ns
System clock fall time tCF 2.0 ns
Mode clock cycle tMOC 256 × tCP ns
Notes 1. The operation of the VR5000 is guaranteed only when the PLL is operating
2. The operation is guaranteed if the internal operating frequency 100 MHz or higher.