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Architecture
129
BLTZL Branch On Less Than Zero Likely BLTZL
31 26 25 21 20 16 15 0
BCOND
000001
rs
BLTZL
00010
offset
6 5 5 16
Format :
BLTZL rs, offset
Description :
Generates a branch target address by adding the address of the instruction in the delay slot to the 16-
bit offset (that has been left-shifted two bits and sign-extended to 32 bits). If the value in general-
purpose register rs is negative (i.e., the sign bit of rs is 1), the program branches to the target address
after a one-cycle delay. If the branch is not taken, the instruction in the delay slot is treated as a
NOP.
Operation :
T:
T + 1:
target ← (offset
15
)
14
|| offset || 0
2
condition ← (GPR[rs]
31
= 1)
if condition then
PC ← PC + target
else
NullifyCurrentInstruction
endif
Exceptions :
None