Architecture
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6.3.7 Overflow exception
• Cause
− A two's complement overflow results from the execution of an ADD, ADDI or SUB instruction.
• Exception mask
The Overflow exception is not maskable.
• Applicable instructions
ADD, ADDI, SUB
• Processing
− The common exception vector (0x8000 0080) is used.
− Ov(12) is set for ExcCode in the Cause register.
− The EPC register points to the address of the instruction causing the exception. If, however,
that instruction is in the branch delay slot (for execution during a branch), the immediately
preceding branch instruction address is retained in the EPC register and the Cause register BD
bit is set to 1.
6.3.8 Reserved Instruction exception
• Cause
− Attempting to execute an instruction whose major opcode (bits 31..26) is undefined, or a special
instruction whose minor opcode (bits 5..0) is undefined.
− Attempting to execute reserved instruction (LWCz and SWCz).
• Exception mask
− The Reserved Instruction exception is not maskable.
• Processing
− The common exception vector (0x8000 0080) is used.
− RI(10) is set for ExcCode in the Cause register.
− The EPC register points to the address of the instruction causing the exception. If, however,
that instruction is in the branch delay slot (for execution during a branch), the immediately
preceding branch instruction address is retained in the EPC register and the Cause register BD
bit is set to 1.
