AMD Confidential
User Manual September 12
th
, 2008
Appendix A 223
Store the entire 64 bits of CR0 to a 64-bit
register.
Store the low 16 bits of CR0 to memory.
Set interrupt flag (IF) to 1.
Store the segment selector from the task
register to a 16-bit general-purpose
register.
Store the segment selector from the task
register to a 32-bit general-purpose
register.
Store the segment selector from the task
register to a 64-bit general-purpose
register.
Store the segment selector from the task
register to a 16-bit memory location.
Exchange GS base with KernelGSBase MSR.
Return from operating system.
Return from operating system.
Raise an invalid opcode exception.
Set the zero flag (ZF) to 1 if the segment
selected can be read.
Set the zero flag (ZF) to 1 if the segment
selected can be written.
Write modified cache lines to main memory,
invalidate internal caches, and trigger
external cache flushes.
Write EDX:EAX to the MSR specified by ECX.
Table 15-9: System Instruction Reference
A.6.3.1 INT – Interrupt to Vector
Interrupt to Debug Vector.
Interrupt to task-gate is not implemented. An attempt to execute an interrupt to
task-gate results in a „FeatureNotImplemented‟ exception and the simulation will
be stopped.
When delivering an exception in an attempt to deliver a hardware interrupt the
simulation will not push the resume-flag (RF) onto the stack.
Always clears VM, NT, TF, and RF bits in rFLAGS.
A.6.3.2 IRET – Return from Interrupt
The simulator does not support nested task-switching using the rFLAGS nested-task bit
(NT) and the TSS back-link field. An interrupt return (IRET) to the previous task (nested-
task) will result in a „FeatureNotImplemented‟ exception and the simulation will be
stopped.
