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Chapter 3 Programming Your Universal Counter for Remote Operation
Elements of SCPI Commands
Programming Guide 3-23
• Bit 5 (ESB) summarizes the Standard Event Status Register.
This bit indicates whether or not one of the enabled Standard Event Status
Register events have occurred since the last reading or clearing of the
Standard Event Status Register.
This bit is set TRUE (one) when an enabled event in the Standard Event
Status Register is set TRUE. Conversely, this bit is set FALSE (zero)
when no enabled events are set TRUE.
• Bit 6 (RQS/MSS) summarizes IEEE 488.1 RQS and Master Summary
Status.
When a serial poll is used to read the Status Byte Register,
the RQS bit indicates if the device was sending SRQ TRUE. The RQS bit
is set FALSE by a serial poll.
When *STB? is used to read the Status Byte Register, the MSS bit
indicates the Master Summary Status. The MSS bit indicates whether or
not the Counter has at least one reason for requesting service.
• Bit 7 (OSB) summarizes the Operation Status Event Register.
This bit indicates whether or not one or more of the enabled Operation
events have occurred since the last reading or clearing of the Operation
Status Event Register.
This bit is set TRUE (one) when an enabled event in the Operation Status
Event Register is set TRUE. Conversely, this bit is set FALSE (zero)
when no enabled events are set TRUE.
Service Request Enable Register
The Service Request Enable Register selects which summary bits in the Status
Byte Register may cause service requests as shown in
Figure 3-7.
Use *SRE to write to this register and *SRE? to read this register.
Use *SRE 0 to clear the register. A cleared register does not allow status
information to generate the service requests. (Power-on also clears this register.)