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ESAI Programming Model
DSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 2
Freescale Semiconductor 6-37
6.3.6.10 SAISR Transmit Frame Sync Flag (TFS) - Bit 13
When set, TFS indicates that a transmit frame sync occurred in the current time slot. TFS is set at the start
of the first time slot in the frame and cleared during all other time slots. Data written to a transmit data
register during the time slot when TFS is set is transmitted (in network mode), if the transmitter is enabled,
during the second time slot in the frame. TFS is useful in network mode to identify the start of a frame.
TFS is cleared by hardware, software, ESAI individual, or STOP reset. TFS is valid only if at least one
transmitter is enabled (i.e. one or more of TE0, TE1, TE2, TE3, TE4 and TE5 are set).
NOTE
In normal mode, TFS always reads as a one when transmitting data because
there is only one time slot per frame – the “frame sync” time slot.
6.3.6.11 SAISR Transmit Underrun Error Flag (TUE) - Bit 14
TUE is set when at least one of the enabled serial transmit shift registers is empty (no new data to be
transmitted) and a transmit time slot occurs. When a transmit underrun error occurs, the previous data
(which is still present in the TX registers that were not written) is retransmitted. If TEIE is set, an ESAI
transmit data with exception (underrun error) interrupt request is issued when TUE is set. Hardware,
software, ESAI individual, and STOP reset clear TUE. TUE is also cleared by reading the SAISR with
TUE set, followed by writing to all the enabled transmit data registers or to TSR.
6.3.6.12 SAISR Transmit Data Register Empty (TDE) - Bit 15
TDE is set when the contents of the transmit data register of all the enabled transmitters are transferred to
the transmit shift registers; it is also set for a TSR disabled time slot period in network mode (as if data
were being transmitted after the TSR was written). When set, TDE indicates that data should be written to
all the TX registers of the enabled transmitters or to the time slot register (TSR). TDE is cleared when the
DSP writes to all the transmit data registers of the enabled transmitters, or when the DSP writes to the TSR
to disable transmission of the next time slot. If TIE is set, an ESAI transmit data interrupt request is issued
when TDE is set. Hardware, software, ESAI individual, and STOP reset clear TDE.
6.3.6.13 SAISR Transmit Even-Data Register Empty (TEDE) - Bit 16
When set, TEDE indicates that the enabled transmitter data registers became empty at the beginning of an
even time slot. Even time slots are all even-numbered slots (0, 2, 4, 6, etc.). Time slots are numbered from
zero to N-1, where N is the number of time slots in the frame. The zero time slot is considered even. This
flag is set when the contents of the transmit data register of all the enabled transmitters are transferred to
the transmit shift registers; it is also set for a TSR disabled time slot period in network mode (as if data
were being transmitted after the TSR was written). When set, TEDE indicates that data should be written
to all the TX registers of the enabled transmitters or to the time slot register (TSR). TEDE is cleared when
the DSP writes to all the transmit data registers of the enabled transmitters, or when the DSP writes to the
TSR to disable transmission of the next time slot. If TIE is set, an ESAI transmit data interrupt request is
issued when TEDE is set. Hardware, software, ESAI individual, and STOP reset clear TEDE.