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DSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 2
Index-2 Freescale Semiconductor
Receive Interrupt Enable Bits 7-14
SHI Control/Status Register 7-10
HDM0-HDM5 (HCKR Divider Modulus Select) 7-9
HEN (HCSR SHI Enable) 7-10
HFIFO (HCSR FIFO Enable Control) 7-12
HFM0-HFM1 (HCKR Filter Mode) 7-9
HI
2
C (HCSR Serial Host Interface I
2
C/SPI Selection)
7-11
HIDLE (HCSR Idle) 7-13
HM0-HM1 (HCSR Serial Host Interface Mode) 7-11
HMST (HCSR Master Mode) 7-12
Host
Receive Data FIFO (HRX)
7-6
Receive Data FIFO—DSP Side 7-6
Transmit Data Register (HTX) 7-6
Transmit Data Register—DSP Side 7-6
Host Receive Data Register (HRX) (FIFO) C-15
HREQ Function In SHI Slave Modes 7-12
HRFF (HCSR Host Receive FIFO Full) 7-16
HRIE0-HRIE1 (HCSR Receive Interrupt Enable) 7-14
HRNE (HCSR Host Receive FIFO Not Empty) 7-15
HROE (HCSR Host Receive Overrun Error) 7-16
HRQE0-HRQE1 (HCSR Host Request Enable) 7-12
HTDE (HCSR Host Transmit Data Empty) 7-15
HTIE (HCSR Transmit Interrupt Enable) 7-14
HTUE (HCSR Host Transmit Underrun Error) 7-15
I
I
2
C 7-1, 7-17
Bit Transfer 7-17
Bus Protocol For Host Read Cycle 7-19
Bus Protocol For Host Write Cycle 7-19
Data Transfer Formats 7-19
Master Mode 7-23
Protocol for Host Write Cycle 7-19
Receive Data In Master Mode 7-24
Receive Data In Slave Mode 7-22
Slave Mode 7-21
Start and Stop Events 7-18
Transmit Data In Master Mode 7-25
Transmit Data In Slave Mode 7-23
I
2
C Bus Acknowledgment 7-18
I
2
C Mode 7-1
Inter Integrated Circuit Bus 7-1
internal buses 1-6
Internal Exception Priorities
SHI
7-5
Internal I/O Memory C-1
interrupt 1-6
interrupt and mode control 2-6, 2-7
interrupt control 2-6, 2-7
Interrupt Priority Register 4-6
Interrupt Priority Register- Peripherals (IPR-P) C-12
Interrupt Priority Register-Core (IPR-C) C-11
interrupt priority registers 4-4
Interrupt Vectors
SHI
7-5
J
JTAG 1-8, 2-13
L
LA register 1-6
LC register 1-6
Loop Address register (LA) 1-6
Loop Counter register (LC) 1-6
M
MAC 1-5
Memory 1-3
memory
bootstrap ROM
3-2
program RAM 3-1
X data RAM 3-3
Y data RAM 3-3
Memory Configuration 1-3
Memory Configurations 3-4
Memory Maps 3-6, 3-7
Mode C (MC) 4-2
mode control 2-6, 2-7
modulo adder 1-5
multiplier-accumulator (MAC) 1-4, 1-5
O
offset adder 1-5
OMR register 1-6
OnCE module 1-8, 2-13
On-Chip Emulation (OnCE) module 1-8
on-chip memory
program
3-1
X data RAM 3-3
Y data RAM 3-3
Operating Mode Register (OMR) 1-6, 4-1, 4-2, C-10
Operating Modes 4-3