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Programmer’s Reference
DSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 2
C-10 Freescale Semiconductor
Figure C-2. Operating Mode Register (OMR)
Chip Operating Modes
MOD(D:A) Reset Vector Description
(
Table 4-1 in Section 4.3, “Operating Modes)
Application:
Date:
Programmer:
Sheet 2 of 5
1514131211109876543210
EBD MB MA
19 18 17 1623 22 21 20
SDTASSEN CDP1 CDP0WRP EOV EUN XYS MD
Core-DMA Priority
CDP(1:0) Core-DMA Priority
00
01
10
11
Core vs DMA Priority
DMA accesses > Core
DMA accesses = Core
DMA accesses < Core
*
0
*
0
*
0
Chip Operating Mode
Register (COM)
System Stack Control
Status Register (SCS)
Extended Chip Operating
Mode Register (COM)
Read/Write
Reset = $00030X
Central Processor
TA Synchronize Select
Stack Extension Space Select
Extended Stack Underflow Flag
Extended Stack Overflow Flag
Extended Stack Wrap Flag
Stack Extension Enable
Memory Switch Mode
MS
External Bus Disable
Stop Delay
ATE APD
Address Priority Disable
Address Tracing Enable
= Reserved, Program as 0
*
0
*
0
*
0
*
0
*
1
*
0
*
1
=Reserved, program as 1