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Programmer’s Reference
DSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 2
Freescale Semiconductor C-11
Figure C-3. Interrupt Priority Register-Core (IPR-C)
CENTRAL PROCESSOR
15 14 13 12 11 10 9 8
76543210
D1L0 IDL2 IDL1 IBL2 IBL1 IBL0 IAL2 IAL1 IAL0D0L1 D0L0
23 22 21 20 19 18 1617
D1L1
IAL2 Trigger
0 Level
1 Neg. Edge
IRQA Mode
IAL1 IAL0 Enabled IPL
00 No—
01Yes0
10Yes1
11Yes2
IBL2 Trigger
0 Level
1 Neg. Edge
IRQB Mode
IBL1 IBL0 Enabled IPL
00 No—
01Yes0
10Yes1
11Yes2
*
IDL0D2L0D2L1D3L0D3L1D4L0D4L1D5L0D5L1
IDL2 Trigger
0 Level
1 Neg. Edge
IRQD Mode
IDL1 IDL0 Enabled IPL
00 No—
01Yes0
10Yes1
11Yes2
0
*
0
*
0
*
0
= Reserved, Program as 0
Application:
Date:
Programmer:
Sheet 3 of 5