Filter
Top Products
Serial Host Interface Programming Model
DSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 2
7-10 Freescale Semiconductor
When HFM[1:0] are cleared, the filter is bypassed (spikes are not filtered out). This mode is useful when
higher bit-rate transfers are required and the SHI operates in a noise-free environment.
When HFM1 = 1 and HFM0 = 0, the narrow-spike-tolerance filter mode is selected. In this mode the filters
eliminate spikes with durations of up to 50ns. This mode is suitable for use in mildly noisy environments
and imposes some limitations on the maximum achievable bit-rate transfer.
When HFM1 = 1 and HFM0 = 1, the wide-spike-tolerance filter mode is selected. In this mode the filters
eliminate spikes up to 100ns. This mode is recommended for use in noisy environments; the bit-rate
transfer is strictly limited. The wide-spike- tolerance filter mode is highly recommended for use in I
2
C bus
systems as it fully conforms to the I
2
C bus specification and improves noise immunity.
NOTE
HFM[1:0] are cleared during hardware reset and software reset.
After changing the filter bits in the HCKR to a non-bypass mode (HFM[1:0] not equal to ‘00’), the
programmer should wait at least ten times the tolerable spike width before enabling the SHI (setting the
HEN bit in the HCSR). Similarly, after changing the I
2
C bit in the HCSR or the CPOL bit in the HCKR,
while the filter mode bits are in a non-bypass mode (HFM[1:0] not equal to ‘00’), the programmer should
wait at least ten times the tolerable spike width before enabling the SHI (setting HEN in the HCSR).
7.4.6 SHI Control/Status Register (HCSR)—DSP Side
The HCSR is a 24-bit read/write register that controls the SHI operation and reflects its status. Each bit is
described in one of the following paragraphs. When in the Stop state or during individual reset, the HCSR
status bits are reset to their hardware-reset state, while the control bits are not affected.
7.4.6.1 HCSR Host Enable (HEN)—Bit 0
The read/write control bit Host Enable (HEN) enables the overall operation of the SHI. When HEN is set,
SHI operation is enabled. When HEN is cleared, the SHI is disabled (individual reset state, see below).
The HCKR and the HCSR control bits are not affected when HEN is cleared. When operating in Master
mode, HEN should be cleared only after the SHI is idle (HBUSY = 0). HEN is cleared during hardware
reset and software reset.
Table 7-3 SHI Noise Reduction Filter Mode
HFM1 HFM0 Description
0 0 Bypassed (Disabled)
01Reserved
1 0 Narrow Spike Tolerance
1 1 Wide Spike Tolerance