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Serial Host Interface Programming Model
DSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 2
7-4 Freescale Semiconductor
Figure 7-4 SHI Programming Model—DSP Side
HCKFR
815 14 13 12 11 10 9
1623 22 21 20 19 18 17
023
SHI Receive Data FIFO (HRX)
(read only, X: $FFFF94)
HRX
SHI Transmit Data Register (HTX)
(write only, X: $FFFF93)
Reserved bit, read as 0, should be written with 0 for future compatibility.
HDM5HFM1
07654321
HDM6HDM7HFM0 HDM2 HDM0HDM1 HRSHDM3HDM4 CPHACPOL
SHI Clock Control Register (HCKR)
X: $FFFF90
023
HTX
815 14 13 12 11 10 9
1623 22 21 20 19 18 17
HEN
07 654321
HM1
HI
2
C
HM0HRQE0 HMSTHRNEHBER HRFFHROE
HBUSY
HRQE1HIDLE
SHI Control/Status Register (HCSR)
HRIE0HRIE1HTUEHTDE HTIE
X: $FFFF91
FIFO (10 Words Deep)
HBIE
HFIFO
815 14 13 12 11 10 9
1623 22 21 20 19 18 17
HA6
07654321
HA3HA4HA5
SHI I
2
C Slave Address Register (HSAR)
X: $FFFF92
HA1
AA0419k new