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ESAI Programming Model
DSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 2
6-26 Freescale Semiconductor
6.3.3.10 RCCR Receiver High Frequency Clock Direction (RHCKD) - Bit 23
The Receiver High Frequency Clock Direction (RHCKD) bit selects the source of the receiver high
frequency clock when in the asynchronous mode (SYN=0), and the IF2/OF2 flag direction in the
synchronous mode (SYN=1).
In the asynchronous mode when RHCKD is set, the internal clock generator becomes the source of the
receiver high frequency clock, and is the output on the HCKR pin. In the asynchronous mode when
RHCKD is cleared, the receiver high frequency clock source is external; the internal clock generator is
disconnected from the HCKR pin, and an external clock source may drive this pin.
When RHCKD is cleared, HCKR is an input; when RHCKD is set, HCKR is an output.
In the synchronous mode when RHCKD is set, the HCKR pin becomes the OF2 output flag. If RHCKD
is cleared, then the HCKR pin becomes the IF2 input flag. See Table 6-1 and Table 6-9.
6.3.4 ESAI Receive Control Register (RCR)
The read/write Receive Control Register (RCR) controls the ESAI receiver section. Interrupt enable bits
for the receivers are provided in this control register. The receivers are enabled in this register (0,1,2 or 3
Table 6-8 FSR Pin Definition Table
Control Bits
FSR Pin
SYN TEBE RFSD
0 X 0 FSR input
0 X 1 FSR output
100 IF1
101 OF1
110 reserved
1 1 1 Transmitter Buffer Enable
Table 6-9 HCKR Pin Definition Table
Control Bits
HCKR PIN
SYN RHCKD
0 0 HCKR input
0 1 HCKR output
10IF2
11OF2