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Serial Host Interface Programming Model
DSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 2
Freescale Semiconductor 7-7
7.4.4.1 HSAR Reserved Bits—Bits 17–0,19
These bits are reserved and unused. They read as 0s and should be written with 0s for future compatibility.
7.4.4.2 HSAR I
2
C Slave Address (HA[6:3], HA1)—Bits 23–20,18
Part of the I
2
C slave device address is stored in the read/write HA[6:3], HA1 bits of HSAR. The full 7-bit
slave device address is formed by combining the HA[6:3], HA1 bits with the HA0 and HA2 pins to obtain
the HA[6:0] slave device address. The full 7-bit slave device address is compared to the received address
byte whenever an I
2
C master device initiates an I
2
C bus transfer. During hardware reset or software reset,
HA[6:3] = 1011 while HA1 is cleared; this results in a default slave device address of 1011_HA2_0_HA0.
7.4.5 SHI Clock Control Register (HCKR)—DSP Side
The SHI Clock Control Register (HCKR) is a 24-bit read/write register that controls the SHI clock
generator operation. The HCKR bits should be modified only while the SHI is in the individual reset state
(HEN = 0 in the HCSR).
NOTE
The programmer should not use the combination HRS = 1 and HDM[7:0] =
00000000, since it may cause synchronization problems and improper
operation (it is therefore considered an illegal combination).
NOTE
The HCKR bits are cleared during hardware reset or software reset, except
for CPHA, which is set. The HCKR is not affected by the Stop state.
The HCKR bits are described in the following paragraphs.
7.4.5.1 Clock Phase and Polarity (CPHA and CPOL)—Bits 1–0
The programmer may select any of four combinations of Serial Clock (SCK) phase and polarity when
operating in the SPI mode (refer to Figure 7-6). The clock polarity is determined by the Clock Polarity
(CPOL) control bit, which selects an active-high or active-low clock. When CPOL is cleared, it produces
a steady-state low value at the SCK pin of the master device whenever data is not being transferred. If the
CPOL bit is set, a high value is produced at the SCK pin of the master device whenever data is not being
transferred.