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DSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 2
Index-4 Freescale Semiconductor
Sixteen-bit Compatibility 3-1
Size register (SZ) 1-6
SP 1-6
SPI 7-1, 7-16
HCSR
Bus Error
7-16
Host Busy 7-16
Host Receive FIFO Full 7-16
Host Receive FIFO Not Empty 7-15
Host Receive Overrun Error 7-16
Host Transmit Data Empty 7-15
Host Transmit Underrun Error 7-15
Receive Interrupt Enable 7-14
Master Mode 7-21
Slave Mode 7-20
SPI Data-To-Clock Timing 7-8
SPI Data-To-Clock Timing Diagram 7-8
SPI Mode 7-1
SR register 1-6
SS 1-6
Stack Counter register (SC) 1-6
Stack Pointer (SP) 1-6
Status Register 1-10
Status Register (SR) 1-6, C-9
System Stack (SS) 1-6
SZ register 1-6
T
TAP 1-8
Test Access Port (TAP) 1-8
Transmitter High Frequency Clock Divider 6-11
V
VBA register 1-6
Vector Base Address register (VBA) 1-6
X
X data RAM 3-3
X Memory Address Bus (XAB) 1-7
X Memory Data Bus (XDB) 1-7
X Memory Expansion Bus 1-6
XAB 1-7
XDB 1-7
Y
Y data RAM 3-3
Y Memory Address Bus (YAB) 1-7
Y Memory Data Bus (YDB) 1-7
Y Memory Expansion Bus 1-7
YAB 1-7
YDB 1-7