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SHI Clock Generator
DSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 2
Freescale Semiconductor 7-3
7.3 SHI Clock Generator
The SHI clock generator generates the serial clock to the SHI if the interface operates in the Master mode.
The clock generator is disabled if the interface operates in the Slave mode, except in I
2
C mode when the
HCKFR bit is set in the HCKR register. When the SHI operates in the Slave mode, the clock is external
and is input to the SHI (HMST = 0). Figure 7-2 illustrates the internal clock path connections. It is the
user’s responsibility to select the proper clock rate within the range as defined in the I
2
C and SPI bus
specifications.
Figure 7-2 SHI Clock Generator
7.4 Serial Host Interface Programming Model
The Serial Host Interface programming model is divided in two parts:
• Host side—see Figure 7-3 below and Section 7.4.1, "SHI Input/Output Shift Register
(IOSR)—Host Side"
• DSP side—see Figure 7-4 and Section 7.4.2, "SHI Host Transmit Data Register (HTX)—DSP
Side" through Section 7.4.6, "SHI Control/Status Register (HCSR)—DSP Side" for detailed
information.
Figure 7-3 SHI Programming Model—Host Side
SHI
HMST
HMST = 0
HMST = 1
SCK/SCL
Divide By
1 or 8
Divide By 1
To
Divide By 256
HRSHDM0–HDM7
SHI Clock
FOSC
Divide
By 2 Controller
Clock
Logic
CPHA, CPOL, HI2C
AA0417k new
0
I/O Shift Register (IOSR)
IOSR
23
AA0418