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ESAI Programming Model
DSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 2
Freescale Semiconductor 6-31
6.3.4.12 RCR Receiver Section Personal Reset (RPR) - Bit 19
The RPR control bit is used to put the receiver section of the ESAI in the personal reset state. The
transmitter section is not affected. When RPR is cleared, the receiver section may operate normally. When
RPR is set, the receiver section enters the personal reset state immediately. When in the personal reset
state, the status bits are reset to the same state as after hardware reset.The control bits are not affected by
the personal reset state.The receiver data pins are disconnected while in the personal reset state. Note that
to leave the personal reset state by clearing RPR, the procedure described in Section 6.6, "ESAI
Initialization Examples" should be followed.
6.3.4.13 RCR Receive Exception Interrupt Enable (REIE) - Bit 20
When REIE is set, the DSP is interrupted when both RDF and ROE in the SAISR status register are set.
When REIE is cleared, this interrupt is disabled. Reading the SAISR status register followed by reading
the enabled receivers data registers clears ROE, thus clearing the pending interrupt.
6.3.4.14 RCR Receive Even Slot Data Interrupt Enable (REDIE) - Bit 21
The REDIE control bit is used to enable the receive even slot data interrupts. If REDIE is set, the receive
even slot data interrupts are enabled. If REDIE is cleared, the receive even slot data interrupts are disabled.
A receive even slot data interrupt request is generated if REDIE is set and the REDF status flag in the
SAISR status register is set. Even time slots are all even-numbered time slots (0, 2, 4, etc.) when operating
in network mode. The zero time slot is marked by the frame sync signal and is considered to be even.
Reading all the data registers of the enabled receivers clears the REDF flag, thus servicing the interrupt.
Receive interrupts with exception have higher priority than receive even slot data interrupts, therefore if
exception occurs (ROE is set) and REIE is set, the ESAI requests an ESAI receive data with exception
interrupt from the interrupt controller.
6.3.4.15 RCR Receive Interrupt Enable (RIE) - Bit 22
The DSP is interrupted when RIE and the RDF flag in the SAISR status register are set. When RIE is
cleared, this interrupt is disabled. Reading the receive data registers of the enabled receivers clears RDF,
thus clearing the interrupt.
Receive interrupts with exception have higher priority than normal receive data interrupts, therefore if
exception occurs (ROE is set) and REIE is set, the ESAI requests an ESAI receive data with exception
interrupt from the interrupt controller.
6.3.4.16 RCR Receive Last Slot Interrupt Enable (RLIE) - Bit 23
RLIE enables an interrupt after the last slot of a frame ended in network mode only. When RLIE is set the
DSP is interrupted after the last slot in a frame ended regardless of the receive mask register setting. When
RLIE is cleared the receive last slot interrupt is disabled. Hardware and software reset clear RLIE. RLIE
is disabled when RDC[4:0]=00000 (on-demand mode). The use of the receive last slot interrupt is
described in Section 6.4.3, "ESAI Interrupt Requests".