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SHI Programming Considerations
DSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 2
Freescale Semiconductor 7-25
In a receive session, only the receive path is enabled and the HTX-to-IOSR transfers are inhibited. If the
HRNE status bit is set, the HRX FIFO contains valid data, which may be read by the DSP using either DSP
instructions or DMA transfers. When the HRX FIFO is full, the SHI suspends the serial clock just before
acknowledge. In this case, the clock will be reactivated when the FIFO is read (the SHI gives an ACK = 0
and proceeds receiving).
7.7.4.2 Transmit Data In I
2
C Master Mode
A transmit session is initiated if the R/W direction bit of the transmitted slave device address byte is
cleared. Following a transmit initiation, the IOSR is loaded from HTX (assuming HTX is not empty) and
its contents are shifted out, MSB-first, on the SDA line. Following each transmitted byte, the SHI
controller samples the SDA line at the ninth clock pulse, and inspects the ACK status. If the transmitted
byte was acknowledged (ACK = 0), the SHI controller continues transmitting the next byte. However, if
it was not acknowledged (ACK = 1), the HBER status bit is set to inform the DSP side that a bus error (or
overrun, or any other exception in the slave device) has occurred. Consequently, the I
2
C master device
generates a stop event and terminates the session.
HTX contents are transferred to the IOSR when the complete word (according to HM0–HM1) has been
shifted out. It is, therefore, the responsibility of the programmer to select the right number of bytes in an
I
2
C frame so that they fit in a complete number of words. Remember that for this purpose, the slave device
address byte does not count as part of the data.
In a transmit session, only the transmit path is enabled and the IOSR-to-HRX FIFO transfers are inhibited.
When the HTX transfers its valid data word to the IOSR, the HTDE status bit is set and the DSP may write
a new data word to HTX using either DSP instructions or DMA transfers. If both IOSR and HTX are
empty, the SHI will suspend the serial clock until new data is written into HTX (when the SHI proceeds
with the transmit session) or HIDLE is set (the SHI reactivates the clock to generate the Stop event and
terminate the transmit session).
7.7.5 SHI Operation During DSP Stop
The SHI operation cannot continue when the DSP is in the Stop state, since no DSP clocks are active.
While the DSP is in the stop state, the following will occur:
• If the SHI was operating in the I
2
C mode, the SHI pins will be disabled (high impedance).
• If the SHI was operating in the SPI mode, the SHI pins will not be affected.
• The HCSR status bits and the transmit/receive paths are reset to the same state produced by
hardware reset or software reset.
• The HCSR and HCKR control bits are not affected.
NOTE
Freescale recommends that the SHI be disabled before entering the Stop
state.