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SPI Bus Characteristics
DSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 2
7-16 Freescale Semiconductor
7.4.6.16 Host Receive FIFO Full (HRFF)—Bit 19
The read-only status bit Host Receive FIFO Full (HRFF) indicates that the Host Receive FIFO (HRX) is
full. HRFF is set when the HRX FIFO is full. HRFF is cleared when HRX is read by the DSP (read
instructions or DMA transfers) and at least one place is available in the FIFO. HRFF is cleared by hardware
reset, software reset, SHI individual reset, and during the Stop state.
7.4.6.17 Host Receive Overrun Error (HROE)—Bit 20
The read-only status bit Host Receive Overrun Error (HROE) indicates that a data-receive overrun error
occurred. Receive-overrun errors can not occur when operating in the I
2
C Master mode, since the clock is
suspended if the receive FIFO is full; it also cannot occur when operating in the I
2
C Slave mode when
HCKFR is set. HROE is set when the shift register (IOSR) is filled and ready to transfer the data word to
the HRX FIFO and the FIFO is already full (HRFF is set). When a receive-overrun error occurs, the shift
register is not transferred to the FIFO. If a receive interrupt occurs with HROE set, the receive-overrun
interrupt vector will be generated. If a receive interrupt occurs with HROE cleared, the regular receive-data
interrupt vector will be generated. HROE is cleared by reading the HCSR with HROE set, followed by
reading HRX. HROE is cleared by hardware reset, software reset, SHI individual reset, and during the Stop
state.
7.4.6.18 Host Bus Error (HBER)—Bit 21
The read-only status bit Host Bus Error (HBER) indicates that an SHI bus error occurred when operating
as a master (HMST set). In I
2
C mode, HBER is set if the transmitter does not receive an acknowledge after
a byte is transferred; in this case, a stop event will be generated and then transmission will be suspended.
In SPI mode, the bit is set if SS is asserted; in this case, transmission is suspended at the end of transmission
of the current word. HBER is cleared only by hardware reset, software reset, SHI individual reset, and
during the Stop state.
7.4.6.19 HCSR Host Busy (HBUSY)—Bit 22
The read-only status bit Host Busy (HBUSY) indicates that the I
2
C bus is busy (when in the I
2
C mode) or
that the SHI itself is busy (when in the SPI mode). When operating in the I
2
C mode, HBUSY is set after
the SHI detects a Start event and remains set until a Stop event is detected. When operating in the Slave
SPI mode, HBUSY is set while SS is asserted. When operating in the Master SPI mode, HBUSY is set if
the HTX register is not empty or if the IOSR is not empty. HBUSY is cleared otherwise. HBUSY is cleared
by hardware reset, software reset, SHI individual reset, and during the Stop state.
7.5 SPI Bus Characteristics
The SPI bus consists of two serial data lines (MISO and MOSI), a clock line (SCK), and a Slave Select
line (SS
).During an SPI transfer, a byte is shifted out one data pin while a different byte is simultaneously
shifted in through a second data pin. It can be viewed as two 8-bit shift registers connected together in a
circular manner, where one shift register is located on the master side and the other on the slave side. Thus
the data bytes in the master device and slave device are effectively exchanged. The MISO and MOSI data
pins are used for transmitting and receiving serial data. When the SPI is configured as a master, MISO is