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Programmer’s Reference
DSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 2
C-18 Freescale Semiconductor
Figure C-10. ESAI Transmit Clock Control Register (TCR)
15 65419 18 17 16 10 9 8 714 13 12 11
TE0
3210
TE2
23 22 21 20
TE1
TE3TE4TE5TSHFDTMOD0TFSLTFSRTEIETEDIETIETLIE
ESAI
TCR - ESAI Transmit Clock Control Register
X: $FFFFB5 Reset: $000000
TWATMOD1TSWS4
TSWS3 TSWS2 TSWS1
TSWS0
PADC
rsvd
TPR
TLIE
0 Transmit Last Slot Interrupt disabled
1 Transmit Last Slot Interrupt enabled
TIE
0 Transmit Interrupt disabled
1 Transmit Interrupt enabled
TEDIE
0 Transmit Even Slot Data Interrupt disabled
1 Transmit Even Slot Data Interrupt enabled
TEIE
0 Transmit Exception Interrupt disabled
1 Transmit Exception Interrupt enabled
TPR
0 Transmitter Normal Operation
1 Transmitter Personal Reset
PADC
0 Zero Padding disabled
1 Zeor Padding enabled
TFSR
0
Word-length frame sync synchronous
to beginning of data word first slot
1
Word-length frame sync 1 clock before
beginning of data word first slot
TFSL
0 Word-length frame sync
1 1-bit clock period frame sync
TE [0:5]
0 Transmitter disabled
1 Transmitter enabled
TSHFD
0 Data shifted out MSB first
1 Data shifted out LSB first
TWA
0 Data left aligned
1 Data right aligned
TMOD1 TMOD0
0 0 Normal mode
0 1 Network mode
10Reserved
11AC97
TSWS [0:4] Defines slot and data word length
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