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SHI Programming Considerations
DSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 2
Freescale Semiconductor 7-23
7.7.3.2 Transmit Data In I
2
C Slave Mode
A transmit session is initiated when the personal slave device address has been correctly identified and the
R/W bit of the received slave device address byte has been set. Following a transmit initiation, the IOSR
is loaded from HTX (assuming the latter was not empty) and its contents are shifted out, MSB first, on the
SDA line. Following each transmitted byte, the SHI controller samples the SDA line at the ninth clock
pulse, and inspects the ACK status. If the transmitted byte was acknowledged (ACK = 0), the SHI
controller continues and transmits the next byte. However, if it was not acknowledged (ACK = 1), the
transmit session is stopped and the SDA line is released. Consequently, the external master device may
generate a stop event in order to terminate the session.
HTX contents are transferred to IOSR when the complete word (according to HM0–HM1) has been shifted
out. It is, therefore, the responsibility of the programmer to select the correct number of bytes in an I
2
C
frame so that they fit in a complete number of words. For this purpose, the slave device address byte does
not count as part of the data, and therefore, it is treated separately.
In a transmit session, only the transmit path is enabled and the IOSR-to-HRX FIFO transfers are inhibited.
When the HTX transfers its valid data word to IOSR, the HTDE status bit is set and the DSP may write a
new data word to HTX using either DSP instructions or DMA transfers.
When HCKFR is cleared, if both IOSR and HTX are empty when the master device attempts a transmit
session, an underrun condition occurs, setting the HTUE status bit; if this occurs, the previous word will
be retransmitted.
When HCKFR is set, if both IOSR and HTX are empty when the master device attempts a transmit session,
the SHI will hold the clock line to GND eliminating the possibility of reaching the underrun error
condition.
The HREQ output pin, if enabled for transmit (HRQE1–HRQE0 = 10), is asserted when HTX is
transferred to IOSR for transmission. When asserted, HREQ indicates that the slave device is ready to
transmit the next data word. HREQ is deasserted at the first clock pulse of the next transmitted data word.
The HREQ line may be used to interrupt the external I
2
C master device. Connecting the HREQ line
between two SHI-equipped DSPs, one operating as an I
2
C master device and the other as an I
2
C slave
device, enables full hardware handshaking.
7.7.4 I
2
C Master Mode
The I
2
C Master mode is entered by enabling the SHI (HEN = 1), selecting the I
2
C mode (HI
2
C = 1) and
selecting the Master mode of operation (HMST = 1). Before enabling the SHI as an I
2
C master, the
programmer should program the appropriate clock rate in HCKR.
When configured in the I
2
C Master mode, the SHI external pins operate as follows:
• SCK/SCL is the SCL serial clock output.
• MISO/SDA is the SDA open drain serial data line.
• MOSI/HA0 is the HA0 slave device address input.
•SS/HA2 is the HA2 slave device address input.
•HREQ is the Host Request input.