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BDSL File
DSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 2
B-4 Freescale Semiconductor
attribute BOUNDARY_LENGTH of DSP56364 : entity is 86;
attribute BOUNDARY_REGISTER of DSP56364 : entity is
-- num cell port func safe [ccell dis rslt]
"0 (BC_1, *, control, 1)," &
"1 (BC_6, GPIO(3), bidir, X, 0, 1, Z)," &
"2 (BC_1, *, control, 1)," &
"3 (BC_6, GPIO(2), bidir, X, 2, 1, Z)," &
"4 (BC_1, *, control, 1)," &
"5 (BC_6, GPIO(1), bidir, X, 4, 1, Z)," &
"6 (BC_1, *, control, 1)," &
"7 (BC_6, GPIO(0), bidir, X, 6, 1, Z)," &
"8 (BC_6, D(7), bidir, X, 12, 1, Z)," &
"9 (BC_6, D(6), bidir, X, 12, 1, Z)," &
"10 (BC_6, D(5), bidir, X, 12, 1, Z)," &
"11 (BC_6, D(4), bidir, X, 12, 1, Z)," &
"12 (BC_1, *, control, 1)," &
"13 (BC_6, D(3), bidir, X, 12, 1, Z)," &
"14 (BC_6, D(2), bidir, X, 12, 1, Z)," &
"15 (BC_6, D(1), bidir, X, 12, 1, Z)," &
"16 (BC_6, D(0), bidir, X, 12, 1, Z)," &
"17 (BC_1, A(17), output3, X, 23, 1, Z)," &
"18 (BC_1, A(16), output3, X, 23, 1, Z)," &
"19 (BC_1, A(15), output3, X, 23, 1, Z)," &
-- num cell port func safe [ccell dis rslt]
"20 (BC_1, A(14), output3, X, 23, 1, Z)," &
"21 (BC_1, A(13), output3, X, 23, 1, Z)," &
"22 (BC_1, A(12), output3, X, 23, 1, Z)," &
"23 (BC_1, *, control, 1)," &
"24 (BC_1, A(11), output3, X, 23, 1, Z)," &
"25 (BC_1, A(10), output3, X, 23, 1, Z)," &
"26 (BC_1, A(9), output3, X, 23, 1, Z)," &
"27 (BC_1, A(8), output3, X, 29, 1, Z)," &
"28 (BC_1, A(7), output3, X, 29, 1, Z)," &
"29 (BC_1, *, control, 1)," &
"30 (BC_1, A(6), output3, X, 29, 1, Z)," &
"31 (BC_1, A(5), output3, X, 29, 1, Z)," &
"32 (BC_1, A(4), output3, X, 29, 1, Z)," &
"33 (BC_1, A(3), output3, X, 29, 1, Z)," &
"34 (BC_1, A(2), output3, X, 29, 1, Z)," &
"35 (BC_1, A(1), output3, X, 29, 1, Z)," &
"36 (BC_1, A(0), output3, X, 29, 1, Z)," &
"37 (BC_1, *, control, 1)," &
"38 (BC_1, AA0, output3, X, 37, 1, Z)," &
"39 (BC_1, *, control, 1)," &
-- num cell port func safe [ccell dis rslt]
"40 (BC_1, AA1, output3, X, 39, 1, Z)," &
"41 (BC_1, *, control, 1)," &
"42 (BC_1, RD_N, output3, X, 41, 1, Z)," &
"43 (BC_1, WR_N, output3, X, 41, 1, Z)," &
"44 (BC_1, *, control, 1)," &
"45 (BC_1, CAS_N, output3, X, 44, 1, Z)," &