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Serial Host Interface Programming Model
DSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 2
Freescale Semiconductor 7-15
NOTE
Clearing HRIE[1:0] will mask a pending receive interrupt only after a
one-instruction-cycle delay. If HRIE[1:0] are cleared in a long interrupt
service routine, it is recommended that at least one other instruction separate
the instruction that clears HRIE[1:0] and the RTI instruction at the end of
the interrupt service routine.
7.4.6.13 HCSR Host Transmit Underrun Error (HTUE)—Bit 14
The read-only status bit Host Transmit Underrun Error (HTUE) indicates that a transmit-underrun error
occurred. Transmit-underrun errors can occur only when operating in the SPI Slave mode or the I
2
C Slave
mode when HCKFR is cleared (in a Master mode, transmission takes place on demand and no underrun
can occur). It is set when both the shift register and the HTX register are empty and the external master
begins reading the next word:
• When operating in the I
2
C mode, HTUE is set in the falling edge of the ACK bit. In this case, the
SHI will retransmit the previously transmitted word.
• When operating in the SPI mode, HTUE is set at the first clock edge if CPHA = 1; it is set at the
assertion of SS if CPHA = 0.
If a transmit interrupt occurs with HTUE set, the transmit-underrun interrupt vector will be generated. If
a transmit interrupt occurs with HTUE cleared, the regular transmit-data interrupt vector will be generated.
HTUE is cleared by reading the HCSR and then writing to the HTX register. HTUE is cleared by hardware
reset, software reset, SHI individual reset, and during the Stop state.
7.4.6.14 HCSR Host Transmit Data Empty (HTDE)—Bit 15
The read-only status bit Host Transmit Data Empty (HTDE) indicates that the HTX register is empty and
can be written by the DSP. HTDE is set when the data word is transferred from HTX to the shift register,
except for a special case in SPI Master mode when CPHA = 0 (see HCKR). When operating in the SPI
Master mode with CPHA = 0, HTDE is set after the end of the data word transmission. HTDE is cleared
when HTX is written by the DSP either with write instructions or DMA transfers. HTDE is set by hardware
reset, software reset, SHI individual reset, and during the Stop state.
7.4.6.15 Host Receive FIFO Not Empty (HRNE)—Bit 17
The read-only status bit Host Receive FIFO Not Empty (HRNE) indicates that the Host Receive FIFO
(HRX) contains at least one data word. HRNE is set when the FIFO is not empty. HRNE is cleared when
HRX is read by the DSP (read instructions or DMA transfers), reducing the number of words in the FIFO
to 0. HRNE is cleared during hardware reset, software reset, SHI individual reset, and during the Stop state.