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ESAI Programming Model
DSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 2
Freescale Semiconductor 6-19
6.3.2.11 TCR Transmit Frame Sync Length (TFSL) - Bit 15
The TFSL bit selects the length of frame sync to be generated or recognized. If TFSL is cleared, a
word-length frame sync is selected. If TFSL is set, a 1-bit clock period frame sync is selected. See
Figure 6-7 for examples of frame length selection.
01011 Reserved
01110
10001
10011
10100
10110
10111
11001
11010
11011
11100
11101
Table 6-5 ESAI Transmit Slot and Word Length Selection (continued)
TSWS4 TSWS3 TSWS2 TSWS1 TSWS0 SLOT LENGTH WORD LENGTH