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Serial Host Interface Programming Model
DSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 2
7-14 Freescale Semiconductor
NOTE
Clearing HBIE will mask a pending bus-error interrupt only after a
one-instruction-cycle delay. If HBIE is cleared in a long interrupt service
routine, it is recommended that at least one other instruction separate the
instruction that clears HBIE and the RTI instruction at the end of the
interrupt service routine.
7.4.6.11 HCSR Transmit-Interrupt Enable (HTIE)—Bit 11
The read/write HCSR Transmit-Interrupt Enable (HTIE) control bit is used to enable the SHI transmit data
interrupts. If HTIE is cleared, transmit interrupts are disabled, and the HTDE status bit must be polled to
determine if the SHI transmit-data register is empty. If both HTIE and HTDE are set and HTUE is cleared,
the SHI will request SHI transmit-data interrupt service from the interrupt controller. If both HTIE and
HTUE are set, the SHI will request SHI transmit-underrun-error interrupt service from the interrupt
controller. HTIE is cleared by hardware reset and software reset.
NOTE
Clearing HTIE will mask a pending transmit interrupt only after a
one-instruction cycle-delay. If HTIE is cleared in a long interrupt service
routine, it is recommended that at least one other instruction separate the
instruction that clears HTIE and the RTI instruction at the end of the
interrupt service routine.
7.4.6.12 HCSR Receive Interrupt Enable (HRIE[1:0])—Bits 13–12
The read/write HCSR Receive Interrupt Enable (HRIE[1:0]) control bits are used to enable the SHI
receive-data interrupts. If HRIE[1:0] are cleared, receive interrupts are disabled, and the HRNE and HRFF
(bits 17 and 19, see below) status bits must be polled to determine if there is data in the receive FIFO. If
HRIE[1:0] are not cleared, receive interrupts will be generated according to Table 7-6.
NOTE
HRIE[1:0] are cleared by hardware and software reset.
Table 7-6 HCSR Receive Interrupt Enable Bits
HRIE[1:0] Interrupt Condition
00 Disabled Not applicable
01 Receive FIFO not empty
Receive Overrun Error
HRNE = 1 and HROE = 0
HROE = 1
10 Reserved Not applicable
11 Receive FIFO full
Receive Overrun Error
HRFF = 1 and HROE = 0
HROE = 1