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DSP56300 Core Functional Blocks
DSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 2
1-6 Freescale Semiconductor
1.5.3 Program Control Unit (PCU)
The PCU performs instruction prefetch, instruction decoding, hardware DO loop control, and exception
processing. The PCU implements a seven-stage pipeline and controls the different processing states of the
DSP56300 core. The PCU consists of the following three hardware blocks:
• Program decode controller (PDC)
• Program address generator (PAG)
• Program interrupt controller (PIC)
The PDC decodes the 24-bit instruction loaded into the instruction latch and generates all signals necessary
for pipeline control. The PAG contains all the hardware needed for program address generation, system
stack, and loop control. The PIC arbitrates among all interrupt requests (internal interrupts, as well as the
five external requests: IRQA, IRQB, IRQD, and NMI), and generates the appropriate interrupt vector
address.
PCU features include the following:
• Position independent code support
• Addressing modes optimized for DSP applications (including immediate offsets)
• On-chip instruction cache controller
• On-chip memory-expandable hardware stack
• Nested hardware DO loops
• Fast auto-return interrupts
The PCU implements its functions using the following registers:
• PC—program counter register
• SR—Status register
• LA—loop address register
• LC—loop counter register
• VBA—vector base address register
• SZ—stack size register
• SP—stack pointer
• OMR—operating mode register
• SC—stack counter register
The PCU also includes a hardware system stack (SS).
1.5.4 Internal Buses
To provide data exchange between blocks, the following buses are implemented:
• Peripheral input/output expansion bus (PIO_EB) to peripherals
• Program memory expansion bus (PM_EB) to program memory
• X memory expansion bus (XM_EB) to X memory