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Operating Modes
DSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 2
Freescale Semiconductor 4-3
4.3 Operating Modes
The operating modes are as shown in Table 4-1 The operating modes are latched from MODA, MODB
and MODD pins during reset. Each operating mode is briefly described below. The operation of all
bootstrap modes is defined by the Bootstrap ROM source code in Appendix A, "Bootstrap ROM".
Mode 4 The DSP starts fetching instructions from the starting address of the on-chip Program
ROM.
Mode 5 The bootstrap program loads instructions through Port A from external byte-wide memory
starting at address P:$D00000. The bootstrap code expects to read 3 bytes specifying the
number of program words, 3 bytes specifying the address to start loading the program
words and then 3 bytes for each program word to be loaded. The number of words, the
starting address and the program words are read least significant byte first followed by the
mid and then by the most significant byte. The program words will be stored in contiguous
PRAM memory locations starting at the specified starting address. After reading the
program words, program execution starts from the same address where loading started. The
SRAM memory access type is selected by the values in Address Attribute Register 1
(AAR1), with 31 wait states for each memory access. Address $D00000 is reflected as
address $00000 on Port A pins A0-A17.
Mode 6 Reserved.
Mode 7 Reserved for Burn-In testing.
Mode C Reserved.
Mode D In this mode, the internal PRAM is loaded from the Serial Host Interface (SHI). The SHI
operates in the SPI slave mode, with 24-bit word width.The bootstrap code expects to read
a 24-bit word specifying the number of program words, a 24-bit word specifying the
Table 4-1 DSP56364 Operating Modes
Mode MOD D MOD B MOD A
Reset
Vector
Description
$4 0 0 0 $FF0000 Jump to PROM starting address
$5 0 0 1 $FF0000 Bootstrap from byte-wide memory
$6 0 1 0 $FF0000 Reserved
$7 0 1 1 $FF0000 Reserved for Burn-in testing
$C 1 0 0 $FF0000 Reserved
$D 1 0 1 $FF0000 Bootstrap from SHI (slave SPI mode)
$E 1 1 0 $FF0000 Bootstrap from SHI (slave I
2
C mode, clock freeze
enabled)
$F 1 1 1 $FF0000 Bootstrap from SHI (slave I
2
C mode, clock freeze
disabled)