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Programmer’s Reference
DSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 2
Freescale Semiconductor C-17
Figure C-9. ESAI Transmit Clock Control Register (TCCR)
TCKP
0 Transmitter Clock Polarity set to clockout on rising edge of
transmitter clock, latch in on falling edge of transmit clock
1 Transmitter Clock Polatiry set to clockout on falling edge of
transmit clock, latch in on rising edge of transmit clock
15 65419 18 17 16 10 9 8 714 13 12 11
TPM0
3210
TPM2
23 22 21 20
TPM1
TPM3TPM4TPM5TPM6TPM7TPSRTDC0TDC1TDC2TDC3TDC4TFP0TFP1TFP2TFP3TCKPTFSPTHCKPTCKDTFSDTHCKD
ESAI
TCCR - ESAI Transmit Clock Control Register
X: $FFFFB6 Reset: $000000
TFP [3:0]
Sets divide rate for transmission high
frequency clock. Range $0-$F (1-16)
TFSP
0 Frame sync polarity positive
1 Frame sync polarity negative
THCKP
0 Transmitter High Frequency Clock Polarity set to clockout
on rising edge of transmit clock, latch on falling edge.
1 Transmitter High Frequency Clock Polarity set to clockout
on falling edge of transmit clock, latch on rising edge.
TCKD
0 External clock source used
1 Internal clock source used
TFSD
0 FST is input
1 FST is output
THCKD
0 HCKT is input
1 HCKT is output
TPSR
0 Divide by 8 prescaler operational
1 Divide by 8 prescaler bypassed
TPM [7:0]
Specifies the prescaler divide rate is
for the transmitter clock generator
Range from $00-FF (1-256).
TDC [4:0]
Divider control. Range $00-FF (1-32)
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