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GPIO Programming Model
DSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 2
5-2 Freescale Semiconductor
5.2.1 Port B Control Register (PCRB)
The read/write Port B Control Register (PCRB) controls the functionality of the GPIO pins in conjunction
with the Port B Direction Register (PRRB).
5.2.1.1 PCRB Control Bits (PC[3:0]) - Bits 3-0
When a PC[i] bit is cleared, the corresponding GPIO[i] pin is three-stated if PDC[i] is cleared, or it is an
output if PDC[i] is set. When a PC[i] bit is set, the corresponding GPIO[i] pin is an input if PDC[i] is
cleared, or it is an open-drain output if PDC[i] is set. Refer to Table 5-1 for a summary of the GPIO
configuration control. Hardware and software reset clear the PC[3:0] bits.
5.2.1.2 PCRB Reserved Bits - Bits 23-4
These bits are reserved and unused. They read as 0s and should be written with 0s for future compatibility.
76543210
PDC3 PDC2 PDC1 PDC0 PRRB
15 14 13 12 11 10 9 8 X:$FFFFCE
23 22 21 20 19 18 17 16
Reserved, read as zero, should be written with zero for future
compatibility
Figure 5-2 GPIO Port B Direction Register (PRRB)
76543210
PD3 PD2 PD1 PD0 PDRB
15 14 13 12 11 10 9 8 X:$FFFFCD
23 22 21 20 19 18 17 16
Reserved, read as zero, should be written with zero for future
compatibility
Figure 5-3 GPIO Port B Data Register (PDRB)