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Programmer’s Reference
DSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 2
C-16 Freescale Semiconductor
Figure C-8. SHI Host Control/Status Register (HCSR)
SHI
*
= Reserved, write as 0
15 14 13 12
11 10 9 8 7 6 5 4 3
2
10
HRQE0 HFIF0 HM1 HM0 HI
2
CHEN
SHI Control/Status
X:$FFFF91
Reset = $008200
Register (HCSR)
19 18 17 1623 22 21 20
HRFFHROEHBUSY
*
0
HMSTHTIE HBIE HIDLE HRQE1HTDE HTUEHRIE1HRIE0HRNEHBER
Host Transmit Underrun Error
Read-Only Status Bit
Host Transfer Data Empty
Read-Only Status Bit
Host Receive FIFO Not Empty
Read-Only Status Bit
Host Receive FIFO Full
Read-Only Status Bit
Host Receive Overrun Error
Read-Only Status Bit
*
0
*
0
HCKFR
Application:
Date:
Programmer:
HRQE1 HRQE0 HRTQE Pin Operation
0 0 High Impedance
0 1 Asserted if OSR ready to receive new word
1 0 Asserted if OSR ready to transmit new word
11
I
2
C:Asserted if OSR ready to transmit or receive
SPI: Asserted if OSR ready to transmit and recieve
HFIFO
0 1 level FIFO
1 10 level FIFO
HM1 HM0
0 0 8 bit data
0 1 16 bit data
1 0 24 bit data
HMST
0 Slave mode
1 Master mode
HCKFR
0 I2C Slave Clock
freeze disabled
1 I2C Slave Clock
freeze enabled
HEN
0 SHI disabled
1 SHI enabled
HI2C
0 SPI mode
HRIE1 HRIE0 Interrupt Condition
0 0 Disabled Not applicable
0 1 Receive FIFO not empty
Receiver Overrun Error
HRNE =1 &HROE=0
HROE=1
10Reserved Not applicable
1 1 Receive FIFO full
Receive Overrun Error
HRFF=1 & HROE=0
HROE=1
HIDL
0Bus busy
1 Stop event
HBIE
0 Bus Error Interrupt disabled
1 Bus error Interrupt enabled
HTIE
0 Transmit Interrupt disabled
HBUSY
I
2
C
SPI Mode
0 Stop event Not Busy
1SHI detects
Start
SS
detected(Slave)
-OR-HTX/IOSR not
empty (master)
HBER
I
2
C
SPI Mode
0 No error No error
1 No acknowledge SS
asserted
Sheet 3 of 3