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External Memory Expansion Port (Port A)
DSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 2
Freescale Semiconductor 2-5
2.5.2 External Data Bus
2.5.3 External Bus Control
Table 2-6 External Data Bus Signals
Signal
Name
Signal Type
State during
Reset
Signal Description
D0–D7 Input/Output Tri-stated Data Bus—D0–D7 are active-high, bidirectional input/outputs that provide the
bidirectional data bus for external program and data memory accesses. D0–D7
are tri-stated during hardware reset and when the DSP is in the stop or wait
low-power standby mode.
Table 2-7 External Bus Control Signals
Signal
Name
Signal
Type
State during
Reset
Signal Description
AA0–AA1/R
AS0–RAS1
Output Tri-stated Address Attribute or Row Address Strobe—When defined as AA, these
signals can be used as chip selects or additional address lines. When defined as
RAS
, these signals can be used as RAS for DRAM interface. These signals are
tri-statable outputs with programmable polarity. These signals are tri-stated
during hardware reset and when the DSP is in the stop or wait low-power standby
mode.
CAS Output Tri-stated Column Address Strobe— CAS
is an active-low output used by DRAM to strobe
the column address. This signal is tri-stated during hardware reset and when the
DSP is in the stop or wait low-power standby mode.