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Serial Host Interface Programming Model
DSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 2
7-6 Freescale Semiconductor
Figure 7-5 SHI I/O Shift Register (IOSR)
7.4.2 SHI Host Transmit Data Register (HTX)—DSP Side
The Host Transmit data register (HTX) is used for DSP-to-Host data transfers. The HTX register is 24 bits
wide. Writing to the HTX register by DSP core instructions or by DMA transfers clears the HTDE flag.
The DSP may program the HTIE bit to cause a Host transmit data interrupt when HTDE is set (see
Section 7.4.6.11, "HCSR Transmit-Interrupt Enable (HTIE)—Bit 11"). Data should not be written to the
HTX until HTDE is set in order to prevent overwriting the previous data. HTX is reset to the empty state
when in Stop mode and during hardware reset, software reset, and individual reset.
In the single-byte data transfer mode the most significant byte of the HTX is transmitted; in the
double-byte mode the two most significant bytes, and in the triple-byte mode all the HTX is transferred.
7.4.3 SHI Host Receive Data FIFO (HRX)—DSP Side
The 24-bit Host Receive data FIFO (HRX) is a 10-word deep, First-In-First-Out (FIFO) register used for
Host-to-DSP data transfers. The serial data is received via the shift register and then loaded into the HRX.
In the single-byte data transfer mode, the most significant byte of the shift register is transferred to the
HRX (the other bits are filled with 0s); in the double-byte mode the two most significant bytes are
transferred (the least significant byte is filled with 0s), and in the triple-byte mode, all 24 bits are
transferred to the HRX. The HRX may be read by the DSP while the FIFO is being loaded from the shift
register. Reading all data from HRX will clear the HRNE flag. HRX may be read by DSP core instructions
or by DMA transfers. The HRX FIFO is reset to the empty state (cleared) when the chip is in Stop mode,
and during hardware reset, software reset, and individual reset.
7.4.4 SHI Slave Address Register (HSAR)—DSP Side
The 24-bit Slave Address Register (HSAR) is used when the SHI operates in the I
2
C Slave mode and is
ignored in the other operational modes. HSAR holds five bits of the 7-bit slave address of the device. The
SHI also acknowledges the general call address (all 0s, 7-bit address, and a 0 R/W bit) specified by the I
2
C
protocol, but will treat any following data bytes as regular data, i.e. the SHI does not differentiate between
its dedicated address and the general call address. HSAR cannot be accessed by the host processor.
16
23
8
15
0
7
8-Bit Data
Mode
16-Bit Data
Mode
24-Bit Data
Mode
Mode of Operation
Stops Data When Data Mode is Selected
Passes Data When Data Mode is Selected
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