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Serial Host Interface Programming Model
DSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 2
Freescale Semiconductor 7-13
7.4.6.9 HCSR Idle (HIDLE)—Bit 9
The read/write control/status bit Host Idle (HIDLE) is used only in the I
2
C Master mode; it is ignored
otherwise. It is only possible to set the HIDLE bit during writes to the HCSR. HIDLE is cleared by writing
to HTX. To ensure correct transmission of the slave device address byte, HIDLE should be set only when
HTX is empty (HTDE = 1). After HIDLE is set, a write to HTX will clear HIDLE and cause the generation
of a stop event, a start event, and then the transmission of the eight MSBs of the data as the slave device
address byte. While HIDLE is cleared, data written to HTX will be transmitted ‘as is.’ If the SHI completes
transmitting a word and there is no new data in HTX, the clock will be suspended after sampling ACK. If
the SHI completes transmitting a word and there is no new data in HTX when HIDLE is set, a stop event
will be generated.
HIDLE determines the acknowledge that the receiver sends after correct reception of a byte. If HIDLE is
cleared, the reception will be acknowledged by sending a ‘0’ bit on the SDA line at the ACK clock tick.
If HIDLE is set, the reception will not be acknowledged (a ‘1’ bit is sent). It is used to signal an end-of-data
to a slave transmitter by not generating an ACK on the last byte. As a result, the slave transmitter must
release the SDA line to allow the master to generate the stop event. If the SHI completes receiving a word
and the HRX FIFO is full, the clock will be suspended before transmitting an ACK. While HIDLE is
cleared the bus is busy, that is, the start event was sent but no Stop event was generated. Setting HIDLE
will cause a stop event after receiving the current word.
NOTE
HIDLE is set while the SHI is not in the I
2
C Master mode.
Care should be taken to ensure that HIDLE be set by the programmer only
after disabling any DMA channel service to HTX.
HIDLE is set during hardware reset, software reset, individual reset, and
while the chip is in the Stop state.
7.4.6.10 HCSR Bus-Error Interrupt Enable (HBIE)—Bit 10
The read/write HCSR Bus-error Interrupt Enable (HBIE) control bit is used to enable the SHI bus-error
interrupt. If HBIE is cleared, bus-error interrupts are disabled, and the HBER status bit must be polled to
determine if an SHI bus error occurred. If both HBIE and HBER are set, the SHI will request SHI bus-error
interrupt service from the interrupt controller. HBIE is cleared by hardware reset and software reset.
1 0 Asserted if IOSR is ready to transmit a new word
11I
2
C: Asserted if IOSR is ready to transmit or receive
SPI: Asserted if IOSR is ready to transmit and receive
Table 7-5 HREQ Function In SHI Slave Modes (continued)
HRQE1 HRQE0 HREQ Pin Operation