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DSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 2
Freescale Semiconductor 6-25
6.3.3.8 RCCR Receiver Clock Source Direction (RCKD) - Bit 21
The Receiver Clock Source Direction (RCKD) bit selects the source of the clock signal used to clock the
receive shift register in the asynchronous mode (SYN=0) and the IF0/OF0 flag direction in the
synchronous mode (SYN=1).
In the asynchronous mode when RCKD is set, the internal clock source becomes the bit clock for the
receive shift registers and word length divider, and is the output on the SCKR pin. In the asynchronous
mode when RCKD is cleared, the clock source is external; the internal clock generator is disconnected
from the SCKR pin, and an external clock source may drive this pin.
In the synchronous mode when RCKD is set, the SCKR pin becomes the OF0 output flag. If RCKD is
cleared, then the SCKR pin becomes the IF0 input flag. See Table 6-1 and Table 6-7.
6.3.3.9 RCCR Receiver Frame Sync Signal Direction (RFSD) - Bit 22
The Receiver Frame Sync Signal Direction (RFSD) bit selects the source of the receiver frame sync signal
when in the asynchronous mode (SYN=0), and the IF1/OF1/Transmitter Buffer Enable flag direction in
the synchronous mode (SYN=1).
In the asynchronous mode when RFSD is set, the internal clock generator becomes the source of the
receiver frame sync, and is the output on the FSR pin. In the asynchronous mode when RFSD is cleared,
the receiver frame sync source is external; the internal clock generator is disconnected from the FSR pin,
and an external clock source may drive this pin.
In the synchronous mode when RFSD is set, the FSR pin becomes the OF1 output flag or the Transmitter
Buffer Enable, according to the TEBE control bit. If RFSD is cleared, then the FSR pin becomes the IF1
input flag. See Table 6-1 and Table 6-8.
Table 6-7 SCKR Pin Definition Table
Control Bits
SCKR PIN
SYN RCKD
0 0 SCKR input
0 1 SCKR output
10IF0
11OF0