Filter
Top Products
ESAI Programming Model
DSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 2
6-30 Freescale Semiconductor
6.3.4.10 RCR Receiver Frame Sync Length (RFSL) - Bit 15
The RFSL bit selects the length of the receive frame sync to be generated or recognized. If RFSL is cleared,
a word-length frame sync is selected. If RFSL is set, a 1-bit clock period frame sync is selected. See
Figure 6-7 for examples of frame length selection.
6.3.4.11 RCR Receiver Frame Sync Relative Timing (RFSR) - Bit 16
RFSR determines the relative timing of the receive frame sync signal as referred to the serial data lines,
for a word length frame sync only. When RFSR is cleared the word length frame sync occurs together with
the first bit of the data word of the first slot. When RFSR is set the word length frame sync starts one serial
clock cycle earlier (i.e. together with the last bit of the previous data word).
11000 32 8
10101 12
10010 16
01111 20
11111 24
01011 Reserved
01110
10001
10011
10100
10110
10111
11001
11010
11011
11100
11101
Table 6-11 ESAI Receive Slot and Word Length Selection (continued)
RSWS4 RSWS3 RSWS2 RSWS1 RSWS0 SLOT LENGTH WORD LENGTH