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DSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 2
Freescale Semiconductor Index-1
Index
A
adder
modulo
1-5
offset 1-5
reverse-carry 1-5
Address Attribute 4-2
address attribute 4-2
Address Generation Unit 1-5
Address Tracing (AT) Mode 4-2
Address Tracing Enable (ATE) 4-2
addressing modes 1-6
AGU 1-5
B
barrel shifter 1-4
Block Diagram 1-2
bootstrap 4-4
bootstrap modes 4-3
Bootstrap Program A-1
bootstrap program options
invoking
4-4
bootstrap ROM 3-2
bus
external address
2-4
external data 2-4
buses
internal
1-6
C
CLKGEN 1-7
Clock 2-4
Clock Control Register (HCKR) C-14
Clock divider 6-11
Clock Generator (CLKGEN) 1-7
configuration 1-3
CPHA and CPOL (HCKR Clock Phase and Polarity
Controls)
7-7
D
data ALU 1-4
registers 1-5
Divide Factor (DF) 1-7
DMA 1-7
DO loop 1-6
DSP56300 core 1-4
DSP56300 Family Manual 1-4
Dynamic Memory 1-8
E
emory 1-3
Enhanced Serial Audio Interface 2-10
ESAI 2-10
ESAI block diagram 6-1
ESAI Common Control Register (SAICR) C-21
ESAI Receive Clock Control Register (RCCR) C-19
ESAI Receive Clock Control Register (RCR) C-20
ESAI Status Register (SAISR) C-22
ESAI Transmit Clock Control Register (TCCR) C-17
ESAI Transmit Clock Control Register (TCR) C-18
external address bus 2-4
external bus control 2-4, 2-6
external data bus 2-4
External Memory 1-9
External Memory Expansion Port 2-4
F
Features 1-2
functional signal groups 2-1
G
Global Data Bus 1-7
Ground 2-3
PLL 2-3
H
HA1, HA3-HA6 (HSAR I
2
C Slave Address) 7-7
hardware stack 1-6
HBER (HCSR Bus Error) 7-16
HBIE (HCSR Bus Error Interrupt Enable) 7-13
HBUSY (HCSR Host Busy) 7-16
HCKR (SHI Clock Control Register) 7-7
HCSR