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SHI Programming Considerations
DSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 2
7-24 Freescale Semiconductor
In the I
2
C Master mode, a data transfer session is always initiated by the DSP by writing to the HTX
register when HIDLE is set. This condition ensures that the data byte written to HTX will be interpreted
as being a slave address byte. This data byte must specify the slave device address to be selected and the
requested data transfer direction.
NOTE
The slave address byte should be located in the high portion of the data
word, whereas the middle and low portions are ignored. Only one byte (the
slave address byte) will be shifted out, independent of the word length
defined by the HM0–HM1 bits.
In order for the DSP to initiate a data transfer the following actions are to be performed:
• The DSP tests the HIDLE status bit.
• If the HIDLE status bit is set, the DSP writes the slave device address and the R/W bit to the most
significant byte of HTX.
• The SHI generates a start event.
• The SHI transmits one byte only, internally samples the R/W direction bit (last bit), and
accordingly initiates a receive or transmit session.
• The SHI inspects the SDA level at the ninth clock pulse to determine the ACK value. If
acknowledged (ACK = 0), it starts its receive or transmit session according to the sampled R/W
value. If not acknowledged (ACK = 1), the HBER status bit in HCSR is set, which will cause an
SHI Bus Error interrupt request if HBIE is set, and a stop event will be generated.
The HREQ input pin is ignored by the I
2
C master device if HRQE1 and HRQE0 are cleared, and
considered if either of them is set. When asserted, HREQ indicates that the external slave device is ready
for the next data transfer. As a result, the I
2
C master device sends clock pulses for the full data word
transfer. HREQ is deasserted by the external slave device at the first clock pulse of the next data transfer.
When deasserted, HREQ will prevent the clock generation of the next data word transfer until it is asserted
again. Connecting the HREQ line between two SHI-equipped DSPs, one operating as an I
2
C master device
and the other as an I
2
C slave device, enables full hardware handshaking.
7.7.4.1 Receive Data in I
2
C Master Mode
A receive session is initiated if the R/W direction bit of the transmitted slave device address byte is set.
Following a receive initiation, data in SDA line is shifted into IOSR MSB first. Following each received
byte, an acknowledge (ACK = 0) is sent at the ninth clock pulse via the SDA line if the HIDLE control bit
is cleared. Data is acknowledged bytewise, as required by the I
2
C bus protocol, and is transferred to the
HRX FIFO when the complete word (according to HM0–HM1) is filled into IOSR. It is the responsibility
of the programmer to select the correct number of bytes in an I
2
C frame so that they fit in a complete
number of words. For this purpose, the slave device address byte does not count as part of the data, and
therefore, it is treated separately.
If the I
2
C slave transmitter is acknowledged, it should transmit the next data byte. In order to terminate the
receive session, the programmer should set the HIDLE bit at the last required data word. As a result, the
last byte of the next received data word is not acknowledged, the slave transmitter releases the SDA line,
and the SHI generates the stop event and terminates the session.