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Programmer’s Reference
DSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 2
C-20 Freescale Semiconductor
Figure C-12. ESAI Receive Clock Control Register (RCR)
15 65419 18 17 16 10 9 8 714 1213 11
RE0
3210
RE2
23 22 21 20
RE1
RE3RsvdRsvdRSHFDRWARFSLRFSRREIEREDIERIERLIE
RFSR Description
0
1
Word-length frame sync synchronous to beginning of
data word first slot
Word-length frame sync 1 clock before beginning of
data word first slot
Description
REDIE Description
0
1
Receive Even Slot Data Interrupt enabled
RIE Description
0
1
Receive Interrupt disabled
Receive Interrupt enabled
RLIE Description
0
1
Receive Last Slot Interrupt disabled
Receive Last Slot Interrupt enabled
REIE Description
0
1
Receive Exception Interrupt disabled
RSWS [0:4] Description
Defines slot and data word length
RFSL
Description
0
1
Receiver disabled
ESAI
RCR - ESAI Receive Clock Control Register
X: $FFFFB7 Reset: $000000
See 8.3.4.9 and table 8-8
RWA Description
0
1
Data left aligned
Diata right aligned
RSHFD Description
0
1
Data shifted in MSB first
Data shifted in LSB first
RE [0:3]
Receiver enabled
Description
0
1
Word length frame sync
1-bit clock period frame sync
Receiver Normal Operation
Receive Exception Interrupt enabled
Receive Even Slot Data Interrupt disabled
RSWS4 RSWS3 RSWS2 RSWS1 RSWS0
RMOD0
RMOD1
RMOD1
Network Mode
Normal mode
0
RMOD0
0
0
0
1
Network mode
Reserved
AC97
1
1
1
Rsvd
Rsvd
RPR
RPR
Receiver Personal Reset
0
1
Application:
Date:
Programmer: