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IXP400 Software
Access-Layer Components: DMA Access Driver (IxDmaAcc) API
Programmer’s Guide IXP400 Software Version 2.0 April 2005
Document Number: 252539, Revision: 007 119
8.7.1 Source Address
Source address is a valid IXP4XX product line and IXC1100 control plane processors memory
map address that points to the first word of the data to be read. The client is responsible to check
the validity of the source address because the access layer and NPE do not have information on the
IXP4XX product line and IXC1100 control plane processors’ memory map.
8.7.2 Destination Address
Destination address is a valid IXP4XX product line and IXC1100 control plane processors’
memory map address that points to the first word of the data to be written. The client is responsible
to check the validity of the destination address because the access layer and NPE do not have
information on the IXP4XX product line and IXC1100 control plane processors memory map.
8.7.3 Transfer Mode
Transfer mode describes the type of DMA transfers. There are four types of transfer modes
supported:
• Copy Only — Moves the data from source to destination.
• Copy and Clear Source — Moves the data from source to destination and clears source to
zero after the transfer is completed.
• Copy and Bytes Swapping (endian) — Moves the data from source to destination. The data
written to the destination is byte swapped. The bytes are swapped within word boundary (for
example, 0x 01 23 45 67 -> 0x 67 45 23 01 where the numbers indicate the source word and
destination byte swapped word in the memory).
• Copy and Bytes Reverse — Moves the data from source to destination. The data written to
the destination is byte reversed. The bytes are swapped across word boundary (for example,
0x 01 23 45 67 -> 0x 76 54 32 10 where the numbers indicate the source word and destination
byte reversed word in the memory).
8.7.4 Transfer Width
Transfer width describes how the data will be transferred across the AHB buses. There are four
transfer widths supported:
• Burst — Data may be accessed in a multiple of word per read or write transactions (normally
used to access 32-bit devices).
• 8-bit — Data must be accessed using an individual 8-bit single transaction (normally used to
access 8-bit devices).
• 16-bit — Data must be accessed using an individual 16-bit single transaction (normally used
to access 16-bit devices).
• 32-bit — Data must be accessed using an individual 32-bit single transaction (normally used
to access 32-bit devices).