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IXP400 Software
Access-Layer Components: Ethernet Access (IxEthAcc) API
April 2005 IXP400 Software Version 2.0 Programmer’s Guide
130 Document Number: 252539, Revision: 007
The data path for each of these devices is accessible via dedicated NPEs. One Ethernet MAC is
provided on each NPE. The NPEs are connected to the North AHB for access to the SDRAM
where frames are stored. The control access to the MAC registers is via the APB Bridge, which is
memory-mapped to the Intel XScale core.
The IxEthAcc component is strictly limited to supporting the internal Ethernet MACs on the
IXP4XX product line and IXC1100 control plane processors.
The services provided by the Ethernet Access component include:
• Ethernet Frame Transmission
• Ethernet Frame Reception
• Ethernet MAC Statistics, Tracking and Reporting
• Ethernet Usage of the IxEthDB Filtering/Learning Database
PHY control is accomplished via the MII interface, which is accessible via the MAC control
registers. This PHY control is not performed by the IxEthAcc component, but rather by the
IxEthMii component. Although mechanisms to set the port operation state have been provided in
the IxEthAcc module, true operating state-link indications should be obtained from IxEthMii.
9.3 Ethernet Access Layers: Architectural Overview
IxEthAcc is not a stand-alone API. It relies on services provided by a number of other components.
The NPE microcode, IxEthDB API and messaging services support IxEthAcc’s primary role of
managing the scheduling, transmission and reception of Ethernet traffic.
9.3.1 Role of the Ethernet NPE Microcode
The Ethernet NPE microcode is responsible for moving data between an Ethernet MAC and
external data memory where it can be made available to the Intel XScale core. In addition, the
Ethernet NPE microcode performs a number of data-processing operations.
There are many possible functions that can be performed by the NPE microcode, some examples of
which are described here. On the Ethernet receive path, the Ethernet NPE microcode performs
filtering (according to the destination MAC address), conversion of frame header data to support
VLAN/QoS or other features, detects specific characteristics about a frame and notifies the client
via IX_OSAL_MBUF header flags, and collects MAC statistics. On the Ethernet transmit path, the
Ethernet NPE microcode can convert the frame header in support of VLAN/QoS or other features,
perform priority queuing of outgoing frames, and collect MAC statistics collection.
It is important to note that the Ethernet NPE microcode support for Ethernet data transport does not
extend to support all Ethernet-related protocols and functions. For example, the NPE microcode
does not automatically detect that a frame is part of an SMB protocol message and prioritize it
automatically above incoming HTTP response data. However, the lack of NPE-level support for
these features in no way inhibits the Intel XScale core-based software from implementing them.
Communication between an Ethernet NPE and the Intel XScale core is facilitated by two
mechanisms. The IxQMgr component is used to handle the data path communications between the
Intel XScale core-based code and NPEs, and is described below. IxNpeMh is used to facilitate the
communication of control-type messages between IxEthAcc and the NPEs.