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IXP400 Software
Buffer Management
Programmer’s Guide IXP400 Software Version 2.0 April 2005
Document Number: 252539, Revision: 007 51
After the NPE modifies the memory, ensure that the Intel XScale core MMU cache is up-to-date by
invalidating cached copies of any parts of the buffer memory that the Intel XScale core will need to
read. It is more robust to invalidate before the NPE gets a chance to write to the SDRAM.
OS-independent macros are provided for both flushing (IX_ACC_DATA_CACHE_FLUSH) and
invalidating (IX_ACC_DATA_CACHE_INVALIDATE). For more information, refer to the header
file ixp_osal/include/IxOsal.h).