Intel IXP400 Frozen Dessert Maker User Manual


 
Intel
®
IXP400 Software
Introduction
Programmer’s Guide IXP400 Software Version 2.0 April 2005
Document Number: 252539, Revision: 007 23
CPU Central Processing Unit
CRC Cyclic Redundancy Check
CSR Customer Software Release
CTR Counter Mode
DDR Double Data Rate
DES Data Encryption Standard
DMT Discrete Multi-Tone
DOI Domain of Interpretation
DSL Digital Subscriber Line
DSP Digital Signal Processor
EEmpty
E1 Euro 1 trunk line (2.048 Mbps)
ECB Electronic Code Book
ECC Error Correction Code
EISA Extended ISA
ERP Endpoint Request Packet
ESP Encapsulation Security Payload (RFC2406)
Eth0 Ethernet NPE A
Eth1 Ethernet NPE B
FFull
FCS Frame Check Sequence
FIFO First In First Out
FRAD Frame Relay Access Device
FRF Frame Relay Forum
FXO Foreign Exchange Office
FXS Foreign Exchange Subscriber
G.SHDSL
ITU G series specification for symmetric High Bit Rate
Digital Subscriber Line
GCI General Circuit Interface
GE Gigabit Ethernet
GFR Guaranteed Frame Rate
GPIO General Purpose Input/Output
HDLC High-Level Data Link Control
HDSL2 High Bit-Rate Digital Subscriber Line version 2
HEC Header Error Check
HLD High Level Design
HMAC Hashed Message Authentication Code
HPI Host Port Interface
HPNA Home Phone Network Alliance
Acronym Description