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IXP400 Software
Access-Layer Components: HSS-Access (IxHssAcc) API
Programmer’s Guide IXP400 Software Version 2.0 April 2005
Document Number: 252539, Revision: 007 191
IxHssAcc presents two “services” to the client application. The Channelized Service presents the
client with raw serial data streams retrieved from the HSS port, while the Packetized Service
provides packet payload data that has been optionally processed according to the HDLC protocol.
IxQMgr is another access-layer component that interfaces to the hardware-based AHB Queue
Manager (AQM). The AQM is SRAM memory used to store pointers to data in SDRAM memory,
which is accessible by both the Intel XScale core and the NPEs. These items are the mechanism by
which data is transferred between IxHssAcc and the NPE. Queues are handled in a different
manner depending on whether packetized or channelized data services are being utilized. The
queue behavior is described in subsequent sections of this chapter.
IxNpeMh is used to allow the IxHssAcc API to communicate to the NPE coprocessors described
below. IxNpeDl is the mechanism used to download and initialize the NPE microcode.
The NPE provides hardware acceleration, protocol handling, and drives the physical interface to
the High-Speed Serial ports. NPE-A is the specific NPE that contains an HSS coprocessor and an
HDLC coprocessor utilized by this API.
13.3.2 Basic API Flow
An overview of the data and control flow for IxHssAcc is shown in Figure 59.
The client initializes and configures HSS using IxHssAcc to configure the HSS port signalling to
match the connected hardware PHY’s or framers. The HSS coprocessor on NPE-A drives the HSS
physical interfaces and handles the sending or receiving of the serial TDM data. Data received on
ports configured for channelized data will be sent up the stack from the HSS coprocessor. Received
Packetized data — with the HDLC option turned on — will be passed to HDLC coprocessor as
appropriate. The IxHssAcc API uses callback functions and data buffers provided by the client to
exchange NPE-to-Intel XScale core data for transmitting or receiving with the help of the IxQMgr
API.