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IXP400 Software
Endianness in Intel
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IXP400 Software
April 2005 IXP400 Software Version 2.0 Programmer’s Guide
342 Document Number: 252539, Revision: 007
It should also be noted that endianness only applies when byte and half-word accesses are made to
memory. If a 32-bit word is read or written to memory, the bit pattern in the memory always
matches the bit pattern in the processor register, regardless of the endianness of the system.
27.2.1 The Nature of Endianness: Hardware or Software?
A processor may be capable of supporting both LE and BE with the active form of endianness
being dependent on bus behavior and the memory systems connected to that bus. Only correct
matching between the processor’s mode, bus mode (that is, how the bus and memory are
connected), and the software will provide correct endian behavior.
Endianness is, in general, a hardware and software issue. However, a processor does not operate in
a vacuum. It is part of a system. This implies that a hardware board with processors and memory
components (unless specially designed to support both endians) would only support one endian
mode, and software on any processor in the system must work with that same endian mode.
27.2.2 Endianness When Memory is Shared
Following the definition of endianness from a software point of view, and assuming a piece of
hardware can be extremely complex and intelligent, can a piece of memory being shared by two
processors running under different endian modes achieve all “IDEAL_BI_ENDIAN” objectives at
the same time? The objectives for such a system are as follows:
• Share long integers correctly.
“Correctly” could be defined as one processor ‘feeling’ that the other processor is under the
same endianness mode as itself. For example, ProcessorBig writes some data starting from it’s
view of address X. Then, if ProcessorLittle reads the same amount of data starting from its
own view of address X, the data read is the same as the data written by ProcessorBig.
• Share short integers correctly.
• Share byte integers correctly.
• Each processor has its own endianness consistency.
Figure 114. 32-Bit Formats
Byte 3 Byte 2 Byte 1 Byte 0
0
31
Memory0x00
32-bit Little-endian memory
Byte 0 Byte 1 Byte 2 Byte 3
0
31
Memory0x00
32-bit Big-endian memory