Intel IXP400 Frozen Dessert Maker User Manual


 
Intel
®
IXP400 Software
Access-Layer Components: HSS-Access (IxHssAcc) API
April 2005 IXP400 Software Version 2.0 Programmer’s Guide
194 Document Number: 252539, Revision: 007
Note: PPM frame length error is calculated from ideal frame frequency.
Figure 60 illustrates a typical T1 frame with active-high frame sync (level) and a posedge clock for
generating data. If the frame pulse was generated on the negedge in the figure, it would be located
one-half clock space to the right. The same location applies if the data was generated on the
negedge of the clock.
Table 40. Jitter Definitions
Jitter Type Jitter Definition
Period Jitter (Pj)
Cycle to Cycle Jitter (Cj)
Wander or Accumulated Jitter (Aj)
Table 41. HSS Frame Output Characterization
HSS Tx Freq. Frame Size (Bits) Actual Frame Length (µs) Frame Length Error (PPM)
512 KHz 32 62.496249 -60.0096
1.536 MHz 96 62.496249 60.016
1.544 MHz 193 125.007499 60.0024
2.048 MHz 256 124.9925 -60.0096
4.096 MHz 512 62.496 -60.0096
8.192 MHz 1024 62.49624 -60.0096
averageii
PeriodPeriodPj =
)()(
)()1()( iii
PjPjCj =
+
=
i
i
PjAj
)(
Figure 60. T1 Tx Signal Format
hss_tx*_data_out
pads_tx*_clock
hss_tx*_frame_out
hss_tx*_data_out_en
FBit data1 data2 data 192data 191 FBit data1
B2377-02