Intel IXP400 Frozen Dessert Maker User Manual


 
Intel
®
IXP400 Software
I
2
C Driver (IxI2cDrv)
April 2005 IXP400 Software Version 2.0 Programmer’s Guide
332 Document Number: 252539, Revision: 007
Enable/disable the driving of the SCL line
I
2
C slave address of the processor
The I
2
C driver features the following hardware and bus status items:
Master transfer error
Bus error detected
Slave address detected
General call address detected
IDBR receive full
IDBR transmit empty
Arbitration loss detected
Slave STOP detected
I
2
C bus busy
I
2
C unit busy
Received/sent status for ACK/NACK
Read/write mode (master-transmit/slave-receive or master-receive/slave-transmit)
Selectable use of internal or OS-provided delay functions.
The I
2
C driver supports single and multi read, single and multi write, and repeated start data
transfers for both interrupt and polled mode. A repeated start data transfer is when the master sends
a start instead of a stop-start to initiate the next transfer. It is different from a multi read or multi
write in that it can allow a read followed by a write or vice versa. Repeated start data transfers in
slave mode are not supported.
The I
2
C hardware does not support extended 10-bit I
2
C addressing; only 7-bit slave addressing is
supported. The driver will allow any 7-bit slave address (0x01 to 0x7F) except 0x00, which is
reserved for general calls.
26.3.2 Dependencies
The I
2
C driver is dependent on the capability provided by the I
2
C hardware. Also, the driver is
dependant upon IxOSAL to provide OS independency. The adapter module provides the Linux
driver interface between the user-space applications and the kernel-space adapter module of the I
2
C
driver. Therefore the adapter module is dependent on the I
2
C algorithm module. VxWorks uses the
I
2
C driver directly and does not need an adapter module.