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IXP400 Software
Programmer’s Guide IXP400 Software Version 2.0 April 2005
Document Number: 252539, Revision: 007 351
MCR p15,0,a1,c1,c0,0
ENDM
The application code built to run on the system must be compiled to match the endianness. Some
compilers generate code in Little-Endian mode by default. To produce the object code that is
targeted for a Big-Endian system, the compiler must be instructed to work in Big-Endian mode. For
example, a
-mbig-endian switch must be specified for GNU* CC since the default operation is in
Little-endian. For GNUPro* assembler,
-EB switch would assemble the code for Big-Endian. The
library being used must have been compiled in the correct endian mode.
27.4.3.3 Little-Endian Data Coherence Enable/Disable
IXP4XX product line and IXC1100 control plane processors allow for MMU control of the
coherence mode used on a per-MMU-page basis. These capabilities are enabled/disabled via the
EXP_CNFG1 register at physical address 0xC4000024.
BYTE_SWAP_EN (Bit 8)
This bit affects only transactions initiated by the Intel XScale core. If Intel XScale core endianness
mode is Little-Endian, then:
• BYTE_SWAP_EN = 1 - The MMU P Bit controls the selection of address or data coherency.
• BYTE_SWAP_EN = 0 - Always address coherence mode if LE selected.
The bit has no effect if the Intel XScale core is in Big-Endian mode.
FORCE_BYTE_SWAP (Bit 9)
The IXP46X product line provides the ability to override any P-attribute bit settings in the page
table. When this bit is set and the Intel XScale core endianness mode is Little-Endian,
BYTE_SWAP_EN is ignored and Data Coherent byte swapping occurs on all transactions. This
can be useful when byte-swapping is required but the MMU is disabled.
This bit is not utilized by the IXP400 software and it not discussed further in this chapter. This bit
is not available on IXP42X product line processors.
EXP_BYTE_SWAP_EN (Bit 10)
The IXP46X product line provides the ability to control whether transfers initiated from master
devices on the Expansion Bus should be byte swapped or not.
This bit is not utilized by the IXP400 software and it not discussed further in this chapter. This bit
is not available on IXP42X product line processors.
27.4.3.4 MMU P-Attribute Bit
The P-Attribute bit is associated with each 1-Mbyte page. The P-Attribute bit is output from the
Intel XScale core with any store or load access associated with that page.